1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same and, more particularly, to a non-volatile memory device and a method of forming the same.
2. Discussion of the Related Art
Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose data stored in memory cells when a power supply is turned off. Non-volatile memory devices retain data stored in memory cells when a power supply is turned off. DRAM and SRAM are examples of volatile memory devices and a flash memory device is an example of a non-volatile memory device.
Flash memory devices comprise a floating gate electrode that stores electrons and a control gate electrode that releases or receives electrons. Flash memory devices can be categorized as having either a split gate structure or a stack gate structure.
FIGS. 1-3 are cross-sectional views showing a method of forming a flash memory device having a spit gate structure.
Referring to FIG. 1, a tunnel oxide layer 2, a floating gate conductive layer 3 and a hard mask layer 4 are sequentially stacked on a semiconductor substrate 1. The tunnel oxide layer 2 may be formed of a thermal oxide layer. The floating gate conductive layer 3 may be formed of a doped polysilicon layer. The hard mask layer 4 is formed of silicon nitride.
The hard mask layer 4 is patterned to form a pair of openings 5 exposing a predetermined region of the floating gate conductive layer 3. A capping layer 6 is formed on the exposed floating gate conductive layer 3 through each of the openings 5. The capping layer 6 is a thermal oxide layer. In this case, the thermal oxide layer 6 is thinner near the sidewall of the openings 5 as compared to a middle portion, the thermal oxide layer 6 having a bird's beak shape.
Referring to FIGS. 2 and 3, the hard mask layer 4 is removed by an etch. Thus, the floating gate conductive layer 3 is exposed. Using the capping layer 6 as a mask, the floating gate conductive layer 3 and the tunnel oxide layer 2 are successively etched until the semiconductor substrate 1 is exposed, thereby forming a tunnel oxide pattern 2a. and a floating gate electrode 3a that are sequentially stacked.
A control gate insulating layer 7 and a control gate conductive layer 8 are sequentially formed on a surface of the semiconductor substrate 1. The control gate insulating layer 7 is formed of silicon oxide and the control gate conductive layer 8 is formed of doped polysilicon.
A photoresist pattern 9 is formed on the control gate conductive layer 8. Using the photoresist pattern 9 as a mask, the control gate conductive layer 8 and the control gate insulating layer 7 are successively patterned to form left and right control gate patterns 10a and 10b, respectively. The left and right control gate patterns 10a and 10b are each located on the semiconductor substrate 1 and a corresponding floating gate electrode 3a. Surfaces of the semiconductor substrate 1 under the left and right control gate patterns 10a and 10b are the left and right control gate channels 11a and 11b, respectively. The left control gate pattern 10a comprises a left control gate insulating pattern 7a and a left control gate electrode 8a. The right control gate pattern 10b comprises a right control gate insulating pattern 7b and a right control gate electrode 8b. Impurity ions are implanted into the semiconductor substrate 1 between the pair of floating gate electrodes 3a, thereby forming a common source region 12.
The left and right control gate patterns 10a and 10b are disposed symmetrically. The pair of floating gate electrodes 3a and the common source region 12 are disposed between the left and right control gate channels 11a and 11b, respectively.
When a misalignment occurs during the formation of the photoresist pattern 9, channel lengths k1 and k2 of the left and right control gate channels 11a and 11b may be different. The difference between the channel lengths k1 and k2 may be increased due to an asymmetrical disposition of the channels 11a and 11b. For example, when the photoresist pattern 9 is misaligned to a left direction by 0.1m, the channel length k1 is decreased by 0.1 μm, but the channel length k2 is increased by 0.1 μm. That is, the difference between the channel lengths k1 and k2 is 0.2 μm. Thus, current flowing through the left and right control gate channels 11a and 11b may not be the same, and left and right cells including the left and right control gate channels 11a and 11b may have different cell characteristics.